RTL Design Engineer
Looking for an RTL Design Engineer - Senior in Boxborough, MA!
9 Month Contract
Competitive Salary!Description:RESPONSIBILITIES:Understand the architecture of the graphics IP and functional block being designed.Work with Architects and shape micro-architecture of digital blocks, write design specification.Work to re-define Power/Performance/Area improvements across design blocks and help set direction of power methodology in future productsDesign at cutting edge speeds (?3G) in the most advanced technology nodesClosely work with block architect to understand design trade-offs and performance challenges.Guide and mentor junior engineers.REQUIREMENTS:Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.Minimum 8 years of digital design experience.Excellent knowledge of Verilog, familiarity with System Verilog for design, Lint, Synthesis, and STA.Experience using industry standard tools and adaptability to utilize home grown tools.Experience with PPA.Good understanding of computer organization/architecture.Strong analytical/problem solving skills and pronounced attention to details.Must be a self-starter and be able to independently drive tasks to completion.Strong interpersonal and communication skills.Experience with Ansys PowerArtist and PTPX is a plus.Prior experience with graphics design/pipelining is a plus.
APPLY NOW for this great opportunity!
Experis is an Equal Opportunity Employer
Job Type:Contract
Location:Boxborough, MADistance:14 miles
Date Posted:Jul 9, 20202 days ago
Industry:IT
Looking for an RTL Design Engineer - Senior in Boxborough, MA!
9 Month Contract
Competitive Salary!Description:RESPONSIBILITIES:Understand the architecture of the graphics IP and functional block being designed.Work with Architects and shape micro-architecture of digital blocks, write design specification.Work to re-define Power/Performance/Area improvements across design blocks and help set direction of power methodology in future productsDesign at cutting edge speeds (?3G) in the most advanced technology nodesClosely work with block architect to understand design trade-offs and performance challenges.Guide and mentor junior engineers.REQUIREMENTS:Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.Minimum 8 years of digital design experience.Excellent knowledge of Verilog, familiarity with System Verilog for design, Lint, Synthesis, and STA.Experience using industry standard tools and adaptability to utilize home grown tools.Experience with PPA.Good understanding of computer organization/architecture.Strong analytical/problem solving skills and pronounced attention to details.Must be a self-starter and be able to independently drive tasks to completion.Strong interpersonal and communication skills.Experience with Ansys PowerArtist and PTPX is a plus.Prior experience with graphics design/pipelining is a plus.
APPLY NOW for this great opportunity!
Experis is an Equal Opportunity Employer