ASIC Design Engineer III
ASIC Design Engineer III - CDC methodology and policy development
Location: Milpitas, CA (95035) - remote to start
Contract Length: 6 months (contract to hire role)
**no sponsorship offered or C2C offered
In this ASIC development position, the individual will be responsible for driving Clock Domain Crossing (CDC) closure across for Western Digital's next generation enterprise SSD SOC controller ASICs. The candidate should possess a deep understanding of the entire ASIC design process from architecture thru timing closure with extensive experience in asynchronous design and clock domain crossing.
Responsibilities:
Work with relevant team member to set up a robust CDC flow and policy
Drive the design team to adherence of the established CDC policies with a goal of having zero waivers
Review and audit designers' modules and CDC reports
Provide expert input in identifying the areas of concerns and how to resolve them
Track and report progress to the SoC lead and management
Drive to a design with zero CDC waivers thru design correction or CDC constraint application
Establish process to review and verify that any constraints are valid and the design is correct with no ambiguity
Skills/Experience:
BS/MS in EE/CE, plus 8+ years of Design experience
RTL/HDL coding in Verilog and proper construction to achieve clean designs that achieve frequency, area and power targets
Understanding of the entire design process from micro-architecture thru GDS with extensive experience in CDC and asynchronous clock domain design.
Excellent verbal and written skills
Team player that can work with peers to achieve desired results
Highly motivated individual that takes ownership and is results oriented
Job Description
In this technical lead/contributor role, essential duties and responsibilities include the following (other duties may be assigned):
Previous technical leadership experience
Proven ability to troubleshoot and analyze complex problems
Ability to multi-task and meet deadlines
Should be a fast learner and a good team player
Comfortable working in a global multi-site ASIC team for enterprise SSD controller development.
Able to work independently, plan tasks/sub-tasks and report progress on weekly basis.
Prior knowledge of scripting languages like Perl, Python or Tcl is a plus.
Additional Qualifications
Must have strong logic design background.
Proficient in RTL (Verilog/VHDL), design verification, and debug.
Proficient in CDC/Lint checking.
Storage or related experience is a plus.
Demonstrated problem solving skills coupled with attention to detail and enthusiasm for a right first time approach.
Language Skills
Ability to read, write and comprehend complex instructions, correspondence, and emails in English.
...
Job Type:Contract
Location:Irvine, CADistance:4 miles
Date Posted:Jan 13, 20216 days ago
Industry:IT
ASIC Design Engineer III - CDC methodology and policy development
Location: Milpitas, CA (95035) - remote to start
Contract Length: 6 months (contract to hire role)
**no sponsorship offered or C2C offered
In this ASIC development position, the individual will be responsible for driving Clock Domain Crossing (CDC) closure across for Western Digital's next generation enterprise SSD SOC controller ASICs. The candidate should possess a deep understanding of the entire ASIC design process from architecture thru timing closure with extensive experience in asynchronous design and clock domain crossing.
Responsibilities:
Work with relevant team member to set up a robust CDC flow and policy
Drive the design team to adherence of the established CDC policies with a goal of having zero waivers
Review and audit designers' modules and CDC reports
Provide expert input in identifying the areas of concerns and how to resolve them
Track and report progress to the SoC lead and management
Drive to a design with zero CDC waivers thru design correction or CDC constraint application
Establish process to review and verify that any constraints are valid and the design is correct with no ambiguity
Skills/Experience:
BS/MS in EE/CE, plus 8+ years of Design experience
RTL/HDL coding in Verilog and proper construction to achieve clean designs that achieve frequency, area and power targets
Understanding of the entire design process from micro-architecture thru GDS with extensive experience in CDC and asynchronous clock domain design.
Excellent verbal and written skills
Team player that can work with peers to achieve desired results
Highly motivated individual that takes ownership and is results oriented
Job Description
In this technical lead/contributor role, essential duties and responsibilities include the following (other duties may be assigned):
Previous technical leadership experience
Proven ability to troubleshoot and analyze complex problems
Ability to multi-task and meet deadlines
Should be a fast learner and a good team player
Comfortable working in a global multi-site ASIC team for enterprise SSD controller development.
Able to work independently, plan tasks/sub-tasks and report progress on weekly basis.
Prior knowledge of scripting languages like Perl, Python or Tcl is a plus.
Additional Qualifications
Must have strong logic design background.
Proficient in RTL (Verilog/VHDL), design verification, and debug.
Proficient in CDC/Lint checking.
Storage or related experience is a plus.
Demonstrated problem solving skills coupled with attention to detail and enthusiasm for a right first time approach.
Language Skills
Ability to read, write and comprehend complex instructions, correspondence, and emails in English.
...