TCS-2295-1 Job Title:Building Engineer Job Description: I
INTAKE NOTES: This is a MOBILE, SHORT TERM Building Engineer assignment for the end client in the San Antonio, TX area. Please include the city and state that the candidate is currently residing at the top of the resume. The assignment is due to coverage for full time employees on leave, and is expected to last until the end of August. A company vehicle will be provided. QUALIFICATIONS: Universal CFC certification is required along with extensive HVAC knowledge to include preventative maintenance and service on HVAC equipment in a commercial setting. General maintenance skills also required to include plumbing, electrical, and carpentry.
Building Engineer, Houston, TX
Universal CFC certification is required along with extensive HVAC knowledge to include preventative maintenance and service on HVAC equipment in a commercial setting.
General maintenance skills also required to include plumbing, electrical, and carpentry. High school diploma or general education degree (GED) and a minimum of four years of related experience and/or trade school training. Universal CFC certification required.
Additional certification in one or more of the following: electrical, mechanical, HVAC and refrigeration systems, process controls, mechanical power transmissions, painting, plumbing, carpentry or engine repair.
Certifications/licenses as may be required by local or state jurisdictions.
Ability to comprehend and interpret instructions, short correspondence, and memos and ask clarifying questions to ensure understanding.
Power Management Engineer - Junior JOB DUTIES:Responsibilities for this position include development, characterization, optimization, and detailed analysis of power and performance benchmarks on Client platforms.EXPERIENCE AND EDUCATION:At a minimum, candidate should possess a Bachelors degree in Computer Engineering or Computer Science with a hardware specialization and 3+ years of experience.Candidate must possess in depth knowledge of system level and CPU level architecture, understanding of system and CPU power architecture, and advanced data analysis skills.Candidate must be familiar with the configuration and operation of power measurement equipment and be able to solder.Experience in power or performance benchmarking and familiarity with CPU performance counter and software profiling tools is strongly desired.Strong understanding of board layout and schematicsCandidate must be an advanced Windows user and be comfortable with writing scripts and automating tasks.Additionally, they must have advanced system building, debug, and OS configuration experience.Setting up test systems for automated test framework.The candidate should be a self-starter and possess excellent communication and interpersonal skills.
Experis is an Equal Opportunity Employer
Responsibilities:Primary daily interface to HQ for scheduling and project tracking.Create and maintain master schedule, and track deliverables for the Austin memory design team in a dynamic, fast pace environment.Gather and organize highly technical information/data for customers, and local teams.Daily collaboration with local team members as well as frequent correspondence w/ overseas teams on various topics. Be an integral part of the memory development team by helping to analyze data, compare against expectations, identify errors/outliers, and then present/document an organized summary/evaluation of the resultsRequirements:A Bachelors degree in EE with minimum 3 years experience in compiler memory development.Expert knowledge of MS Excel and PowerPoint.Perl and Linux shell scripting Be able and willing to participate in occasional off-hours conference calls (usually evening calls) and possible overseas travel.Familiarity with major CAD/EDA tools, especially Cadence Virtuoso.
Experis Engineering is seeking a Library, Technology & Design Flow Co-Optimization Engineer for our client in either Austin, TX or San Jose, CA. This is a direct-hire/perm opportunity with leading semiconductor manufacturer. Immediate need. Relocation package. Sponsorship available.
What you'll be doing:
Explore and demonstrate improved block PPA through library, technology, and design methodology and flow co-optimization on company's advanced process technologies (22nm/16nm/7nm/5nm).
Explore and innovate on company's design platform. Work towards co-optimizing standard cell library, design methodology and flows to show improved block performance.
Work closely with Design Flow team at company headquarters to gain a deep understanding of design methodology & flow, technology capabilities and constraints.
Create several physical design implementations of standardized reference blocks to compare and contrast various tradeoffs between the different optimization techniques that will yield better overall gains in company's technology.
Root-cause design flow issues and independently develop Innovative solutions for design flows and design methodology challenges, validate and document solutions.
Work closely with EDA (Electronic Design Automation) vendors to develop and demonstrate value in new design flows and strategies.
Internalize customer problems and have the grit to solve them in stipulated time constraints
Who we are seeking:
Responsibilities: Hands on development of compiler memories, with a focus on characterization and flow development. Daily collaboration with local team members as well as frequent correspondence w/ overseas teams on various topics. Analyze data, compare against expectations, identify errors/outliers, and then present/document an organized summary/evaluation of the results. May perform other duties as assigned including special projects and other administrative responsibilities.
A Bachelors degree in E.E. with minimum 3 years experience in compiler memory development.
The following work experience will be the most helpful:
Experience with latest technologies and the challenges they present Scripting and flow design and maintenance Timing and Power characterization of compiler memories Race condition and margin characterization and analysis Be able and willing to participate in occasional off-hours conference calls (usually evening calls) and possible overseas travel.
Develop Software/Firmware functions to Initialize Client's Power Server Memory Debug and resolve Software/Firmware and Hardware interaction failures Develop Software tools to enable Memory Characterization activities using various programming languages such as Perl, Python, C/C++ Execute electrical, functional, and system tests of DDR4 memory sub-system test plans as part of a post-silicon Power-System Memory Engineering team. Verify system functionality to product specification using hardware and software validation tools, oscilloscopes, and logic analyzers. Develop technical test plans to support system level bring-up and the validation execution of DDR4 memory subsystem. Analyze & debug electrical and functional test data to drive into production risk-call decisions.scripting and memory experience highly preferred.
Experis is an Equal Opportunity Employer
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