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ASIC Design Verification Engineer

Category:Contract
Location: Milpitas, California 95035
Posted:Wed, May 08, 2019
Salary:Up to US$0.0 per hour
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Experis has an immediate need for a ASIC Design Engineer for our IT Client in San Jose, CA with the following qualifications:

Who You Are:
You collaborate closely with verification engineers, designers, hardware and cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up.

Responsibilities include:
Architect block, cluster and top level DV environment infrastructure
Maintaining existing DV environments and enhancing them Ensuring complete verification coverage through implementation and review of code and functional coverage
Working closely with designers
Emulation effort Be responsible for ASIC bring up

Education and Experience
Bachelors or Masters degree in EE
10+ years of ASIC Verification experience

Knowledge and Skills:
You are proficient in ASIC verification using UVM/System Verilog.
You are proficient in verifying complex blocks, clusters and top level for SoC
You can build test benches from scratch
You are familiar with Perl and/or Python scripting
You have the ability to collaborate with cross-functional teams, and possess the drive to learn and grow
Formal verification (iev/vc formal) knowledge is a plus
Experience of verification using C++ is a plus

Please send your resume in response to this JOB TITLE for IMMEDIATE consideration

Experis is an Equal Opportunity Employer (EOE/AA)

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